Various computer bus protocols support low power states and specify wakeup sequences for individual devices to wake up other linked devices prior to communication. For example, the PCI Express (PCIe) standard provides certain protocols for link power management. The power management (PM) controller of a PCIe device responds to system software to transition through “D-states”. In particular, after system reset, a PCIe device transitions to an uninitialized configuration state D0. Next, the system software completes the enumeration process. After enumeration, the PCIe device transitions to an active D0 state. The PCIe standard defines the power management state of the link based on a particular D-state of a downstream PCIe device.
A PCIe device transitions through link states (L-states), depending on the status and activity of the link. The PCIe standard defines link power management, L0, L0s (L0 standby), L1, L2, and L3. For additional power savings, a PCIe device changes its operation from the fully operative L0 state, to an increased latency, low power L1 state, and ultimately to an off-link L3 state.
The PCIe standard also defines Active State Power Management (ASPM). ASPM is based on a Physical Layer (PHY) protocol to place an idle bus link in a low-power communication state, and ASPM supports L-state transitions. A PCIe device following the ASPM hardware-based protocol supports L-state transitions even when operating in the active D0 state. According to ASPM protocol, a PCIe device reduces its power consumption on its side of the link, and instructs a downstream PCIe device to reduce power on the downstream side of the link.
When a PCIe device begins to transition from the low power communication L1 state to the fully operative L0 state, the PCIe device will exchange training sequences with a downstream PCIe device. A PCIe device provides encoded training sequences using 8b (bit)/10b encoding when the data rate is 2.5 GT/s (gigatransfers per second) or 5.0 GT/s. A PCIe device provides encoded training sequences using a per-lane code along with Physical Layer encapsulation for data rates greater than or equal to 8.0 GT/s. Training sequences include information such as the skew between all lanes within a multi-lane link. When both PCIe devices transition to the L0 state, the PCIe devices have enabled their ability to transmit active traffic on the link.
The PCIe standard defines three discrete logical layers, the Transaction Layer, the Data Link Layer, and the Physical Layer. The Transaction Layer manages Transaction Layer Packets (TLPs) between the Physical Layers of two PCIe devices. The Data Link Layer manages the link and the integrity of the data transferred on the link. Also, the Data Link Layer transmits and receives link management Data Link Layer Packets (DLLPs). For a PCIe device, the PHY includes all circuitry for interface operation, such as the transmitter, the receiver, and the logic to control the power state transitions.
Continued performance pressure has led to increasing requirements for lower latency communication and improved power management for PCIe devices. It would be desirable for PCIe devices to decrease the period of time to transition between power management states.